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Nvidia has one surprising new rival: the world's largest storage vendor

Seagate logo
(Image credit: Seagate)

Hard disk drive manufacturer Seagate has announced that it has designed two processors based on the open RISC-V instruction set architecture. 

The new hardware could further shake up the chipmaking space, which is still reeling from the news of Nvidia’s $40 billion takeover of ARM.

The announcement of the two cores was made at the virtual RISC-V Summit 2020 and marks the first public report on the results of Seagate’s several years of collaboration with RISC-V International. Seagate has also confirmed that one of the cores will be designed for high performance, while the other will be area-optimized.

Chipping away

The high-performance processor promises triple the performance for real-time, critical HDD workloads compared to current solutions, while the area-optimized core offers impressive footprint and power savings. More importantly, however, many are speculating on what the two cores could mean for the ARM architecture that Seagate has typically employed.

Although Nvidia has promised that ARM architecture will continue to be made available for other manufacturers, there are concerns that it will not be quite so open following the takeover. As a result, some firms are exploring RISC-V architecture, which is royalty-free.

Although the RISC-V space has not exactly surged in popularity, it is quietly building momentum, with the likes of Qualcomm, Samsung, Alibaba and even Nvidia itself using the architecture in their chips. The Seagate news will only serve to boost the RISC-V market further.

“Having shipped close to one billion cores over the last year, Seagate has developed significant expertise in system-on-a-chip design,” said Cecil Macgregor, Vice President of Application-Specific Integrated Circuit (ASIC) Development at Seagate. 

“We have now expanded the capability to add customized RISC-V cores to our portfolio, which is critical to future products. We live in a time of unprecedented growth of enterprise data—and much of this data is in motion. These cores will allow devices to share a common RISC-V ISA. Using open security architectures, they will enable more secure movement of data.”